1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly relates to an operational amplifier suitable to drive a capacitive load.
2. Description of the Related Art
An operational amplifier is conventionally formed from bipolar transistors. However, in recent years, the operational amplifier is often formed from MOS transistors because of the necessity of coexistence with a MOS circuit and the request of a low power. It is possible to employ a circuit configuration of the operational amplifier of the MOS transistors by using the analog characteristics peculiar to the MOS transistors, and the configuration is different from the operational amplifier of the bipolar transistors. As one of the application fields of the operational amplifier of the MOS transistors, there is a TFT_LCD (Thin Film Transistor Liquid Crystal Display) driver LSI. This LCD driver LSI contains a plurality of operational amplifiers each having a voltage follower configuration as buffer circuits. In particular, a device having a small offset voltage difference between the plurality of operational amplifiers is required. This is because the characteristics of the TFT LCD causes even the voltage difference of 10 mV to be recognized as a different gradation by the eye of a human. Thus, this field requires the MOS operational amplifier of the very small offset voltage.
FIG. 1 is a circuit diagram showing the configuration of the operational amplifier disclosed in Japanese Laid Open Patent Publication (JP-A-Showa, 61-35004). This conventional operational amplifier is a typical amplifier with a class AB output circuit and includes a driver circuit 1, P-channel MOS transistors 2 and 3, N-channel MOS transistors 4 and 5 and constant current sources 8 and 9. The output of the driver circuit 1 is connected to a drain of the P-channel MOS transistor 2, a source of the N-channel MOS transistor 4, a gate of the N-channel MOS transistor 5 and a constant current source 9 to drive the output circuit based on a signal supplied to an input terminal. The other end of the constant current source 9 is connected to a negative voltage power source VSS2. A source of the N-channel MOS transistor 5 is also connected to the negative voltage power source VSS2, and a drain thereof is connected to an output terminal VOUT and a drain of the P-channel MOS transistor 3. A source of the P-channel MOS transistor 3 is connected to a positive voltage source VDD2, and a gate thereof is connected to the constant current source 8, a source of the P-channel MOS transistor 2 and a drain of the N-channel MOS transistor 4. The other end of the constant current source 8 is also connected to the positive voltage source VDD2. A gate of the P-channel MOS transistor 2 is connected through a constant voltage source 6 to the positive voltage source VDD2, and biased lower by a constant voltage than the positive voltage source VDD2. A gate of the N-channel MOS transistor 4 is connected through a constant voltage source 7 to the negative voltage power source VSS2 and biased higher by a constant voltage than the negative voltage power source.
When this amplifier is used as an operational amplifier, the driver circuit 1 is usually constituted of a differential amplifier. FIG. 2 shows a circuit example of the differential amplifier. This differential amplifier includes P-channel MOS transistors 10 and 11 of a differential pair, N-channel MOS transistors 12 and 13 of a current mirror circuit, and a constant current source 14. Gates of the P-channel MOS transistors 10 and 11 are connected to a negative inversion input terminal Vin (−) and a positive input terminal Vin (+), respectively. The constant current source 14 is connected between sources of the P-channel MOS transistors 10 and 11 and the positive voltage source VDD2. A source of the N-channel MOS transistor 12 is connected to the negative voltage power source VSS2, and a gate and drain are connected to a drain of the P-channel MOS transistor 10. A source of the N-channel MOS transistor 13 is connected to the negative voltage power source VSS2, and a gate is connected to a gate of the N-channel MOS transistor 12, and a drain thereof is connected to a drain of the P-channel MOS transistor 11. A node to which the drain of the P-channel MOS transistor 11 and the drain of the N-channel MOS transistor 13 are connected serves as an output terminal Vout1 of the differential amplifier. The output terminal Vout1 serves as the output of the driver circuit 1 and is connected to the gate of the N-channel MOS transistor 5 of the amplifier shown in FIG. 1. The differential input signals, which are applied to the negative input terminal Vin (−) and the positive input terminal Vin (+), are received by the P-channel MOS transistors 10 and 11. The outputs from the differential pair appear in the drains of the P-channel MOS transistors 10 and 11. The differential output signals are supplied to the current mirror circuit (the N-channel MOS transistors 12 and 13) serving as the active load. The N-channel MOS transistors 12 and 13 convert the differential output signals into a single end signal, which is outputted from the output terminal Vout1. At this differential stage, the input voltage range is represented by the following equation when the input voltage is assumed to be Vin.0<Vin<VGS(10/11)+VDS(sat)(14) Here, VGS(10/11) is the voltage between the gate and the source of each of the P-channel MOS transistors 10 and 11, and VDS(sat)(14) is the voltage between the drain and the source at the saturation point of the P-channel MOS transistor of the constant current source 14. Outside this range, the voltage between the drain and the source of the MOS transistor of the constant current source 14 cannot be generated. Thus, a current I of the constant current source 14 is 0. Therefore, the differential stage does not operate outside this range.
On the contrary, an example of a circuit that insures the operations in the whole voltage range is a so-called Rail-to-Rail amplifier shown in FIG. 3. This differential amplifier includes P-channel MOS transistors 19 and 20 of a P-channel differential pair 31; N-channel MOS transistors 21 and 22 of an N-channel differential pair 32; N-channel MOS transistors 23 and 24 of a current mirror circuit 35; P-channel MOS transistors 15 and 16 of a current mirror circuit 33; P-channel MOS transistors 17 and 18 of a current mirror circuit 34; and constant current sources 25 and 26.
The negative input terminal Vin (−) and the positive input terminal Vin (+) are connected to gates of the P-channel MOS transistors 19 and 20 and gates of the N-channel MOS transistors 21 and 22, respectively. Sources of the P-channel MOS transistors 19 and 20 are commonly connected to each other and connected through a constant current source 26 to the positive voltage source VDD2. Drains of the P-channel MOS transistors 19 and 20 are connected to drains of the N-channel MOS transistors 23 and 24, respectively, and further connected to drains of the P-channel MOS transistors 18 and 15. Gates of the N-channel MOS transistors 23 and 24 are commonly connected to each other and further connected to the drain of the N-channel MOS transistor 23 and serves as an input terminal of the current mirror circuit 35. Also, sources of the N-channel MOS transistors 23 and 24 are commonly connected to each other and connected to the negative voltage power source VSS2 as the common terminal of the current mirror circuit 35. Sources of the N-channel MOS transistors 21 and 22 are commonly connected to each other and connected through a constant current source 25 to the negative voltage power source VSS2. Drains of the N-channel MOS transistors 21 and 22 are connected to the input terminals of the current mirror circuits 33 and 34, respectively. The input terminal of the current mirror circuit 33 is the node to which the gates of the P-channel MOS transistors 15 and 16 are commonly connected and connected to the drain of the P-channel MOS transistor 16. The sources of the P-channel MOS transistors 15 and 16 are commonly connected and connected to the positive voltage source VDD2 as the common terminal of the current mirror circuit 33. The input terminal of the current mirror circuit 34 is the node to which the gates of the P-channel MOS transistors 17 and 18 are commonly connected and connected to the drain of the P-channel MOS transistor 17. The sources of the P-channel MOS transistors 17 and 18 are commonly connected to each other and connected to the positive voltage source VDD2 as the common terminal of the current mirror circuit 34. The node where the drains of the P-channel MOS transistors 15 and 20 and N-channel MOS transistor 24 are commonly connected is the output terminal Vout2 of this differential amplifier (the driver circuit 1) and connected to the gate of the N-channel MOS transistor 5 in FIG. 1.
This circuit serves as the differential stage where the P-channel differential pair 31 and the N-channel differential pair 32 are combined. Thus, the output of the P-channel differential pair 31 and the output of the N-channel differential pair 32 are required to be added. For this reason, the respective drains of the transistors constituting the N-channel differential pair 32 are connected to the input terminals of the respective current mirror circuits 33 and 34. The currents outputted from the output terminals of the current mirror circuits 33 and 34 flow through the respective drains of the N-channel MOS transistors 24 and 23, and the outputs are added. Consequently, in case of the voltage range in which the P-channel differential pair 31 does not operate, the N-channel differential pair 32 operates. On the contrary, in case of the voltage range in which the N-channel differential pair 32 does not operate, the P-channel differential pair 31 operates. Thus, the differential stage operating in the whole voltage range is obtained.
In order to use such a driver circuit 1 so that the output stage of the operational amplifier circuit shown in FIG. 1 carries out the operation of the so-called class AB, an idling current is required to flow through the P-channel MOS transistor 3 and the N-channel MOS transistor 5. The current value is determined by the P-channel MOS transistor 2, the N-channel MOS transistor 4, the constant current sources 8 and 9 and the constant voltage sources 6 and 7, which constitute an operational point setting circuit. At this time, the voltages of the constant voltage sources 6 and 7 are set such that the respective drain currents of the P-channel MOS transistor 2 and N-channel MOS transistor 4 are equal to each other. That is, each drain current is a half of the current flowing out from the constant current source 8. At this time, the idling current of the P-channel MOS transistor 3 at the output stage is set by the constant voltage source 6 and the voltage between the gate and the source of the P-channel MOS transistor 2 biased by the current which is a half of the current of the constant current source 8.
Also, the current which flows out from the constant current source 8 flows through the P-channel MOS transistor 2 and the N-channel MOS transistor 4 into the constant current source 9. When the constant current values of the constant current sources 8 and 9 are different, the current corresponding to the difference flows in from the node between the constant current sources 8 and 9 or flows out from the node. Thus, it could be understood that when the constant current values of the constant current sources 8 and 9 are made equal to each other, the current does not flow into the output of the driver circuit 1. This fact is very important when the driver circuit 1 is configured from the circuit shown in FIG. 2 or 3. That is, it is supposed that the output current flows into the driver circuit 1 as shown in FIG. 2 or 3. Then, a differential offset voltage corresponding to the current is generated. Specifically, when a mutual conductance of the differential transistor is assumed to be gm and the current flowing to the output is assumed to be Iout, the differential offset voltage Vos is obtained from the following equation. Thus, in order to prevent the generation of the offset voltage, the constant current values of the constant current sources 8 and 9 are required to be equal to each other.Vos=Iout/gm 
As mentioned above, the conventional circuit requires the current value matching performance between the constant current source 8 and the constant current source 9, in order to couple the amplifying circuit shown in FIG. 2 or 3 as the driver circuit of the differential amplifier shown in FIG. 1. However, when this differential amplifier is configured inside LSI, it is difficult to match the elements perfectly due to the deviation in the property between the respective elements. That is, the variation in the property between the respective elements causes the differential current between the constant current source 8 and the constant current source 9 to flow into the output terminal (the Vout1 in FIG. 2 and the Vout2 in FIG. 3) in the driver circuit 1. Thus, the offset voltage is generated.